1. Field of the Invention
The present invention relates to a semiconductor device that suppresses latch-up by decreasing the resistance of a base region.
2. Background Art
Semiconductor devices called “power devices,” such as IGBTs (Insulated Gate Bipolar Transistors), have been improved to handle high voltages and large currents and widely used with power control apparatuses for use, for instance, in bullet trains and in the fields of transportation and industrial equipment.
The above semiconductor devices control a large current by performing switching operations such as turn-on and turn-off. It is desired that a switching operation be performed in a region called a safe operating area (SOA). The SOA is defined as a safety operating area where a semiconductor device turns on and turns off. More specifically, the SOA defines a range within which the operating locus of a collector current (Ic) and collector-emitter voltage (Vce) is confined. The SOA is defined in accordance with Ic rating and Vce rating. The SOA for defining the Ic-Vce operating locus prevailing at turn-off is particularly called a reverse bias SOA (RBSOA). For example, a snubber circuit of an actual IGBT or other semiconductor device is designed so as not to exceed the above SOA.
From the viewpoint of safe semiconductor device operations, it is essential that semiconductor device switching take place within the RBSOA or other SOA. However, holes may be accumulated in a p-type base layer so that the base layer charges up. It is conceivable that a thyristor parasitically formed in a semiconductor device may turn on, as a result of such charge-up, to cause a latch-up phenomenon. When such a phenomenon occurs, the SOA may be exceeded to damage the semiconductor device.
As a method of suppressing the above-mentioned latch-up phenomenon, a scheme for suppressing the ON operation of a parasitic thyristor by forming a p-type high-concentration region in a body region is disclosed, for instance, in JP-A-2001-308328.
The aforementioned method of suppressing a latch-up phenomenon, which is disclosed in JP-A-2001-308328, forms a new P+ layer in a base region. The addition of such a P+ layer affects the threshold voltage and various other characteristics of a semiconductor device. This is true not only of the configuration disclosed in JP-A-2001-308328 but also of a case where the resistance of the base region is to be decreased by increasing, for instance, the impurity concentration of the base layer itself. As seen from the above, it is necessary to form the P+ layer while considering the characteristics that vary with impurity profile changes in the base layer. Therefore, there has been a trade-off between providing latch-up suppression by the sacrifice of optimization of various characteristics of a semiconductor device and optimizing various characteristics of a semiconductor device by the sacrifice of adequate latch-up suppression.